1. Field of the Invention
The present invention relates to voltage converters and, more specifically, to a converter enabling a conversion of switched-mode voltage step-up or boost type in parallel with a conversion of switched-mode voltage inversion type (with respect to a reference, generally the ground) (buck-boost).
2. Discussion of the Related Art
FIG. 1 partially and schematically shows a pixel 1 of a monochrome LCD screen or a sub-pixel of a color LCD screen of the type to which the present invention more specifically applies. Each pixel 1 is formed of a control switch M (typically a thin-film MOS transistor, TFT) and of a capacitance C1 as a memory cell. A first conduction terminal of switch M is connected to a column conductor Col, common to all switches in the display screen column. The other conduction terminal of switch M is connected to a first electrode of capacitance C1 of the pixel, having its second electrode connected to ground, the dielectric of capacitance C1 being formed of the liquid crystal used for the display and of a storage capacitor in parallel (not shown). The gates of switches M are connected, in rows, to row conductors Row. The presence of switch M generates a Miller-effect capacitive element C between its gate and its source, and thus between row Row and the first electrode of capacitance C1 of cell 1. Column conductors Col are driven by a column control circuit 2 (C DRIVER) generally setting the luminance reference levels while row conductors Row are driven in scan mode by a row control circuit 3 (R DRIVER).
For a color screen, each cell 1 forms a sub-pixel of a color pixel and the color is provided by a corresponding chromatic filter (RGB) arranged in front of each sub-pixel.
FIG. 2 schematically and partially shows the equivalent electric diagram of a liquid crystal display 10 and of its row driver. In the example of FIG. 2, only two columns Coli and Coli+1 have been shown. Similarly, only five rows Row1, Row2, Row3, Rown−1, and Rown have been shown. The integration of the display on a substrate generally made of glass is no longer limited to the cells but also concerns the row drivers. These drivers comprise, for each row, an RS-type flip-flop B1, B2, B3, . . . Bn−1, and Bn having a direct Q output used to control a switch KR1, KR2, KR3, KRn−1, KRn placed on each row conductor to bring a power supply voltage thereon. The S activation input of first flip-flop B1 receives a scan start signal Start. The S activation input of flip-flop B2 is connected to row Row1, downstream of switch KR1 with respect to the power source, the S activation input of flip-flop B3 is connected to row Row2, downstream of switch KR2, etc., until the S activation input of last flip-flop Bn connected to row Rown−1, downstream of switch KRn−1. The R reset inputs of the flip-flops are respectively connected to the conductor of the row of next rank, downstream of the corresponding flip-flop KR, until the R input of last flip-flop Bn which is looped back on row Row1.
The rows are generally powered by a row scanning. The rows of odd rank Row1, Row3, . . . , Rown−1 are all connected upstream of switches KR1, KR3, . . . KRn−1 to a terminal 32 while the rows of even rank Row2, . . . . Rown are, upstream of their respective switches, connected to a terminal 33. Terminals 32 and 33 are respectively connected to the junction points of pairs of switches Q1 and Q2, respectively Q3 and Q4, series-connected between terminals of application of a respective high turn-on voltage VON and low turn-off voltage VOFF.
The scanning is performed row by row, starting, for example, from an odd row by turning on switches Q1 and Q4 and turning off switches Q2 and Q3 so as to, at the same time, supply this odd row and force the turning-off of the even row of next rank. Signal Start applied to the S activation input of first flip-flop B1 enables an automatic row scanning. The addressing of an even row is performed symmetrically by turning off switches Q1 and Q4 and by turning on switches Q2 and Q3. Switches Q1 to Q4 are thus switched at the rate of the row scanning under control of a circuit 5 (CTRL).
To avoid power losses that are too high, a charge recovery stage is generally provided, which enables, for each column, to use the power stored in the pixels to be turned off in the row which has just been addressed, to help the lighting of the pixels of the next row. For this purpose, terminals 32 and 33 are generally connected by an assembly of two antiparallel diodes D1 and D2, each in series with a resistor R1 and R2 and a switch S1 and S2 controlled by circuit 5.
Before the screen is powered up, signal Start is activated to initialize all flip-flops B1 to Bn, after which the signal disappears to enable to start the scanning. To turn on the pixels of the first odd row, switches Q1 and Q4 are turned on, which causes the application of a voltage VON on terminal 32 and of a voltage VOFF on terminal 33. A current can then flow to charge the capacitances of pixels of this first row. At the end of this addressing period, transistors Q1 and Q4 are turned off, switch S1 is turned on and switch S2 is turned off during a so-called power recovery or transfer phase, which enables to precharge the next (even) row with the discharge of the odd row which has just been addressed. This phase sets the first odd and even rows to an intermediary equilibrium voltage. Then, switches Q2 and Q3 are turned on to pull the voltage of the even row to level VON and end the discharge of the first odd row to level VOFF. At the end of the lighting of the first even row, switches Q2 and Q3 are turned off, switches S2 is turned on and switch S1 is turned off to enable a precharge of the next odd row and thus resume the operation by turning-on of switches Q1 and Q4.
For the same screen resolution, that is, an identical ratio between the number of rows and the number of columns, it is generally desired to increase the number of rows and to decrease the number of columns. Indeed, row drivers which manage the power supply are generally less complex than column drivers which manage data and, further, row drivers are generally integrated on the glass for cost reasons. However, the use of many integrated row control circuits on glass implies the need for a power supply capable of providing a significant power.
It is thus desired to provide a power supply that can generate voltages VON and VOFF and can provide a high power, from a single D.C. voltage. For this purpose, the use of chopper or switched-mode devices enabling either a conversion of boost or pull-up type, or a conversion of buck-boost type is known.
FIG. 3 illustrates a known circuit 40 that can generate voltages VON and VOFF based on a D.C. input signal Vin. Circuit 40 comprises a first portion 42 providing a boost converter intended to generate voltage VON and a second portion 44 forming a buck-boost converter intended to generate voltage VOFF. Portions 42 and 44 are connected in parallel on input signal Vin.
Boost converter 42 comprises, between the terminals of application of voltage Vin, a series connection of an inductance Lb and of a switch Mb controlled by a signal Kb, a terminal of the switch being grounded. A diode Db having its anode connected to the junction point of inductance Lb and switch Mb and having its cathode connected to a first terminal of a capacitor Cb, the second terminal of capacitor Cb being grounded is placed in parallel with switch Mb. Output voltage VON of converter 42 is measured across capacitor Cb.
Buck-boost converter 44 comprises, between the terminals of application of voltage Vin, a series association of a switch Mbb controlled by a signal Kbb and of an inductance Lbb having one of its terminals connected to ground. A diode Dbb having its cathode connected to the junction point of switch Mbb and inductance Lbb, and having its anode connected to a first terminal of a capacitor Cbb, the second terminal of the capacitor being grounded is placed in parallel with inductance Lbb. Voltage VOFF is measured across capacitive element Cbb.
To perform the conversions by chopping, switches Mb and Mbb are controlled to be turned off and on at high frequency, typically from several tens to several hundreds of kilohertz, which enables storing magnetic power in each of inductances Lb and Lbb when the associated switches are turned on and to output this power from converters 42 and 44 when the associated switches are off. Continuously, boost converter 42 delivers a voltage VON having a value greater than voltage Vin and buck-boost converter 44 delivers a voltage VOFF which is smaller than voltage Vin and negative.
A circuit such as shown in FIG. 3 has the disadvantage of comprising two inductive elements which are, be it in integrated circuit technology or on glass, extensive electronic elements, and thus expensive. Thus, there is a need for a circuit that can generate, from a single D.C. voltage, a regulated voltage of higher value and a regulated voltage having a sign opposite to that of this D.C. voltage using a single inductive element.